ENEE244 (Section 0201, 0202, 0203) Digital Logic Design by P. Petrov
Fall 2006
There will be a review section for the final exam on Tuesday (12/19) in ENGR
Building Lecture Hall, Room 1110, at 3:30pm.
The Final Exam will be held on December 20 (Wednesday), 8:00a-10:00a in the class room.
The Third Midterm will be held on November 20 (Monday) in class.
The Second Midterm will be held on October 25 (Wednesday) in class.
Class Information
Instructor: Peter Petrov, AVW 1421, ppetrov at ece dot umd dot edu
Class hours: MWF 10:00am - 10:50pm, JMP 3201
Office hours: MW 11:00am - 12:00pm, AVW 1421
Required text: "Digital Principles and Design", by D. Givone
Course Syllabus
Practice problems
Midterm-1:
Chapter 2:
2.3bd, 2.4ac, 2.10acf, 2.14ad, 2.17ac, 2.18b, 2.19d, 2.22c, 2.23b, 2.25b (for 2's complement only), 2.29, 2.34a, 2.42a, 2.44bc
Chapter 3: 3.3b, 3,5b, 3.6, 3.7b, 3.8, 3.9b, 3.10c, 3.14a, 3.16b, 3.17b, 3.18a, 3.19a, 3.25a, 3.26a, 3.27a, 3.28a
Midterm-2
Problem Set 1:
Chapter 4: 4.2bc, 4.4cd, 4.6bc, 4.7bc, 4.8cdg, 4.9ceh, 4.10abc, 4.11deh, 4.12bchi, 4.16, 4.24
Problem Set 2:
4.25bd, 4.27b, 4.29, 4.30, 4.31, 4.32, 4.33a, 4.34ad, 4.35be, 4.37bc
Midterm-3
Problem Set 1:
5.1ac, 5.2, 5.3, 5.4, 5.8, 5.10ab, 5.11ab, 5.15, 5.16, 5.18, 5.19, 5.21b, 5.22a, 5.24a, 5.27, 5.29, 5.30, 5.31a
Problem Set 2:
6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.11, 6.14, 6.21, 6.23, 6.25, 6.27
Final Exam Practice Problems:
7.1, 7.2, 7.4, 7.5, 7.6, 7.7, 7.14, 7.17, 7.19, 7.20, 7.22, 7.23
Lecture Notes
Binary Adders and Subtracters
Comparators and Decoders
Multiplexers
Programmable Logic Devices (PLDs)
Sequential Networks; Latches
Edge-Triggered Flip-Flops
Registers and Counters
Analysis of Sequential Networks
